Embodiments of the invention relate generally to semiconductor device packages or electronics packages and to a device-almost last method of manufacturing thereof. An embedded device module with a complex semiconductor device or chip (with hundreds or thousands of I/O terminals) is embedded under a prefabricated multilayer interconnect structure, with the semiconductor device attached to the prefabricated multilayer interconnect structure after it is tested thereby avoiding committing the semiconductor device to an interconnect structure with a potential defect. Two different types of interconnects are used to connect the device to the interconnect structure—a high density, moderate performance connection for signal pads and a high performance, moderate density connection for high performance controls, power, and ground pads. Minimal interconnect processing is performed after the semiconductor device is attached, thereby increasing yield and lowering costs while attaining the high electrical performance inherent with an embedded device structure.
State of the art electronics packaging covers a wide range of methods, structures, and approaches from wire bond modules to flip chip modules and to embedded device/chip modules. Wire bonded modules are a mature packaging approach that is low cost but has poor electrical performance and has limited input/output (I/O) capability. These modules use wires bonded to device pads to connect the top I/O pads of semiconductor devices to an interconnect structure such as a multilayered organic or ceramic substrate with multiple dielectric and patterned metal layers. An exemplary construction of a prior art wire bond electronics package 10 is illustrated in FIG. 1 with two semiconductor devices 11 mounted onto a multilayer substrate 13 using die attach material 15 on topside 17. Wire bonds 21 connect die pads 23 located on the active surface 25 of semiconductor devices 11 to conductive pads 27 on the topside 17 of multilayer substrate 13. Molding resin 29 encapsulates semiconductor devices 11, wire bonds 21, and exposed portions of multilayer substrate 13. Multilayer substrate 13 has backside terminals 31 that are connected to conductive pads 27 by through holes 33. Multilayer substrate 13 may have multiple dielectric layers 35, multiple buried conductor layers 37, and multiple layer to layer vias 39. Wire bonds have inherently high inductance and series resistance, current crowding on the bond pads, and can cause microcracking within the semiconductor devices 11 near bonding sites. They are limited to I/O pads in one to three rows of die pads 23 located on the perimeter edges of the devices 11 and typically are limited to a few hundred I/Os.
Prior art flip chip modules use an array of terminal pads dispersed over the full surface of the semiconductor device to interconnect the device I/Os to a package or substrate. The device I/O pads can be in a fully populated array of pads or in a partially depopulated array of pads. Solder bumps are formed on each pad forming an array of solder spheres that are used to flip attach the device onto a package base, substrate, or board that has a matching array of pads. Although the pitch of the solder pads is larger than the pitch of wire bond pads, the array pads utilize the whole device surface and can contain 5× to 20× more pads than a wire bonded device. The solder bumps have larger cross-sections than wire bonds (>20×) and have a much shorter electrical path (>10×) than wire bonds and therefore have higher current carrying capability (>5×) and higher frequency capability (5X). A general construction of a prior art flip chip electronic package 40 is illustrated in FIG. 2 with two semiconductor devices 11 attached to multilayer substrate 13. Flip chip solder bumps 41 are applied to conductive pads 27 on multilayer substrate 13 and coupled to die pads 23. Molding resin 29 encapsulates the semiconductor devices 11. While flip chip modules such as that illustrated in FIG. 2 provide some advantages over wire bond technology, solder has poor electrical conductivity and is susceptible to both solder fatigue and electro-migration failures and the flipped chip has a very poor thermal cooling pathway.
Embedded device or chip modules and Fan-Out Wafer Level Packages (WLPs) are packaging approaches that address the limitations of wire bond and flip chip packages by eliminating wire bonds and solder bumps and replacing them with direct metallization contacts. Embedded device modules and Fan-Out WLPs are moving into the mainstream of microelectronics packaging for low and mid-complexity semiconductor devices, with these approaches being driven by the latest portable electronics devices, such as smart phones, as each new generation of smart phones puts more function into a smaller space with the requirement that the electronics consume less power. Embedded device modules combine multiple electronic devices, such as semiconductor devices or chips, capacitors, resistors and/or inductors in a common package using an interconnect structure that overlies the components and provides direct metallurgical interconnect to component terminals that minimizes interconnect parasitics. Combining multiple electronic devices in the same embedded device module with its lower parasitics provides higher electrical performance, faster operation, and lower power dissipation, while reducing the function's footprint saving board space. Fan-Out WLPs fan out the semiconductor device I/O terminals from the restricted area of the device surface to a larger footprint by fabricating an overlay interconnect structure on the surface of the semiconductor device that extends over an off-device molded region. This allows device I/O pitch to be relaxed to a larger I/O terminal pitch that facilitates attachment to a printed circuit board (PCB). The larger pitch reduces PCB complexity and lowers its costs and increases its yields. It also increases assembly yields, further lowering costs. Fan-Out WLPs can be used as stand-alone surface mounted devices or they can include feed throughs that enable incorporation into Package-on-Package (POP) assembly.
A general construction of a prior art embedded device electronic package 50 is illustrated in FIG. 3 with two semiconductor devices 11 attached to multilayer overlay insulating substrate structure 51. Multilayer overlay insulating substrate structure 51 has multiple insulating substrate layers 53 and multiple wiring layers 55. Structure 51 also includes lower overlay insulating substrate layer 57 with first microvia connections 59 extending through lower overlay insulating substrate layer 57 to die pads 23 of semiconductor devices 11 and connect them to buried wiring layer 61. An upper overlay insulating substrate layer 63 with second microvia connections 65 extends through the upper overlay insulating substrate layer 63 to buried wiring layer 61 and connecting to topside wiring layer 67. Molding resin 29 encapsulates the semiconductor devices 11. The multilayer overlay insulating substrate structure 51 with its direct metallization to die pads 23 through first microvia connections 59 eliminate 90% of the interconnect parasitics associated with wire bonded modules and flip chip modules. Most importantly, interconnect structure defects such as wiring shorts and opens and high resistance or open microvia would cause the scrapping of good semiconductor device that are attached to a die site that had an interconnect defect.
A general construction of a prior art Fan-Out Wafer Level Package (WLP) 70 is depicted in FIG. 4 with one semiconductor device 11 molded into resin material 29. An overlay insulating substrate structure 54 lies over the active surface 25 of the semiconductor device 11 and the top surface 73 of resin material 29. Generally, the process of forming the Fan-Out WLP 70 starts with embedding semiconductor device 11 in resin material 29 with top surface 73 of resin material 29 generally level with active surface 25 of semiconductor device 11. This processing takes place in large circular or rectangular panels in a multi-up configuration. Following this encapsulation, a first overlay insulating substrate layer 57 is applied over the active surface 25 of semiconductor device 11 and the top surface 73 of resin material 29. First microvias 75 are formed through the first overlay insulating substrate layer 57 to die pads 23 and optionally, to feed through conductors 77 that may be embedded in the resin material 29. First wiring layer 61 is applied to the first overlay insulating substrate layer 57 and into first microvias 75 and forming first microvia connections 59 to die pads 23 and optionally, to feed through conductors 77. Second overlay insulating substrate layer 63 is applied to first overlay insulating substrate layer 57 and first wiring layer 61. Second microvias 79 are formed in the second overlay insulating substrate layer 63 to portions of first wiring layer 61. Top side wiring layer 67 is applied to the second overlay insulating substrate layer 63 and into second microvias 79 and forming second microvia connections 65 to exposed portions of first wiring layer 61. Additional overlay insulating substrate layers and wiring layers can be applied for as needed for more complex, higher I/O pad count devices. Optionally, the molding resin 29 can be back ground to planarize and/or thin the module.
Fan-Out WLP 70, with its direct metallization to die pads 23 through first microvia connections 59 eliminate 90% of the interconnect parasitics associated with wire bonded fan-out modules and flip chip fan-out modules. The main disadvantages of the Fan-Out WLP is that interconnect defects that cause the Fan-Out WLP overlay structure to be defective, such as for example interconnect shorts or opens or via opens, causes the costly complex semiconductor device to be scrapped along with the interconnect structure, increasing the effective cost of the packaging process.
Despite the advantages of an embedded device module or Fan-Out WLP construction, these construction techniques are more complex, less mature, and higher cost than wire bond and flip chip approaches. One major disadvantage of the embedded device module construction versus the wire bond or flip chip modules is that defects in the overlay interconnect structure can lead to the loss of a complex and costly semiconductor device since the device is committed to the module prior to the fabrication of the build-up interconnect structure. Prior art approaches to address the yield issues associated with embedded device module construction have had limited effects and/or are not applicable to high performance semiconductor devices with high I/O count and high power and ground current requirements.
Accordingly, it would be desirable to provide an electronics packaging technology that permits construction of a high performance, high I/O count microelectronics package, with high interconnect performance and high interconnect and assembly yield.